Project Description

The Challenge of PAM4 Signal Integrity

PAM4 and 400 Gbps Ethernet

As Ethernet network speeds progressed from 100 Gbps to the new standard of 400 Gbps, a significant step was taken to adopt a 4-Level Pulse Amplitude Modulation (PAM4) encoding scheme instead of the previous 2-level Non-Return-to-Zero (NRZ) encoding. This major change has created a new world of challenges for signal integrity engineers as they approached the task of printed circuit board (PCB) design. This Technology Brief outlines the differences between NRZ and PAM4 encoding and examines some of the techniques and tools used to solve the complex PAM4 signal integrity issues.

What is a PAM4 Signal?

With a 50 Gbps lane rate being the fundamental basis of reaching 400 Gbps, a major decision was made to change the signal-encoding scheme for the new 400G Ethernet standard. Previously, all Ethernet standards used the simple 2-level NRZ method for encoding a binary data stream into a transmittable electrical signal. To attain a higher lane data rate, a 4-Level PAM4 encoding scheme was chosen, which effectively doubles the amount of data transmitted in the same amount of time.

If you think of binary data represented by a signal with two voltages, one voltage for a “0” and the other voltage for a “1”, then this describes the NRZ encoding method. For PAM4 encoding, the signal has four voltage levels, which encodes two binary bits per voltage level. A method known as “Gray coding” combines the most significant bit (MSB) and least significant bit (LSB) pairs in a data stream into one of the four voltage levels. Gray coding helps to reduce the bit errors in the signal caused by voltage amplitude noise. It is easy to see how with two data bits mapped to one voltage level, double the information is transmitted in the same amount of time.

PAM4 Signal vs NRZ

From signal integrity perspective, the four-level PAM4 signaling provides many challenges for printed circuit board (PCB) design. For example, the PAM4 voltage levels are tighter spaced leading to a much worse Signal-to-Noise Ratio (SNR). In fact, due to further nonlinear signal degradation the SNR loss for PAM4 signals is around 11 dB. The low SNR also makes PAM4 signals more vulnerable to amplitude degradations of all types, including inter symbol interference (ISI) and crosstalk. In addition, PAM4 signals have to perform within acceptable limits for insertion loss and return loss, as illustrated in the following diagrams.

pam4 signal diagrams

To achieve seamless data communication between transceivers, the Optical Internetworking Forum (OIF) have defined Common Electrical I/O (CEI) standards for PAM4 signals in PCB design. The table below summarizes the main specifications for the CEI-56G-PAM4 standards.

Standard Description Channel Loss BER (pre-FEC)
CEI-56G-PAM4-VSR Chip-to-module, < 10cm, one connector < 10dB@14 GHz < 1e-6
CEI-56G-PAM4-MR Chip-to-chip, < 50cm, one connector < 20dB@14 GHz < 1e-6
CEI-56G-PAM4-LR Chip-to-chip over backplane, < 100cm, two connectors < 30dB@14 GHz < 1e-4

Note that the PAM4 channel standards allow for a relatively high bit error ratio (BER) of 1e-6 (or 1 error for every 106 bits), this is because forward error correction (FEC) is mandatory for PAM4. FEC is a technique used for correcting errors when data is transmitted over noisy or unreliable channels. Specifically, PAM4 uses Reed Solomon FEC to achieve a corrected BER of <1e-15 per channel.

In addition, signal equalization is required at the transmitter and receiver of channels to help correct signal distortion effects. PAM4 designs use a combination of CTLE (continuous time linear equalization) and FFE (feed-forward equalization) methods.

PAM4 Eye Diagram Analysis

Signal eye diagrams are used to give a visual check on the quality of a channel. If the signal “eye” is clearly visible (open), then the channel quality is good. If the eye is not so clear (closed), then the channel has problems, which will be reflected by a high BER.

For NRZ signals, there is only one eye per unit interval, but for PAM4 signals there are three. This fact highlights the additional problems that PAM4 faces; misalignment of the three eyes due to skew or compression. Note that a PAM4 signal’s three eyes are not symmetrical. The middle eye is the most symmetric vertically, but the top and bottom eyes are very asymmetrical.

The specific eye height (EH) and eye width (EW) are defined for a signal 1e-6 BER. Eye measurement involves first finding the timing center of the middle eye, then measuring the three eye heights at that time. The eye widths are then measured at the bisectors of the eye heights. The CEI-56G-PAM4 standards specify the minimum required eye heights and widths at various PCB test points to ensure a signal BER of 1e-6.

insertion loss return loss pam4 signal

Solving the Challenge of PAM4 PCB Design

After covering the PAM4 signal integrity basics, many issues and challenges remain for PCB design. One primary concern being that of meeting the required OIF and IEEE specifications while still keeping costs low.

In any PCB design, physical layout constraints also come into play. With a high number of differential pairs that need to be routed on a PCB, there needs to be limits placed on trace lengths and widths, and the distance between pairs. A design therefore tends to be a tradeoff between minimizing signal losses and finding space within a PCB’s dimensions. In addition, other mechanical and thermal concerns need to be addressed, which often has an impact on placement.

PAM4 signals are particularly vulnerable to crosstalk, where signal traces close together cause interference in an adjacent trace. In particular, the PCB vias (conductive tube holes that join traces on different PCB layers) are one of the main areas where crosstalk issues arise. A “victim” via often has many aggressors nearby, which has the effect of closing eye diagrams. Special care and attention to via design is required to minimize crosstalk and maintain signal integrity. Some other techniques and tools used for meeting the complex challenge of PAM4 signal integrity can be summarized as follows:

  • Selecting the lowest cost PCB laminate for a particular application
  • Minimizing crosstalk using the optimum BGA package and connector breakouts
  • Using High Frequency Structure Simulator (HFSS) 3D field solver-based coupled via design for electrically transparent vias
  • Creating electrically transparent interconnect designs for minimal reflections
  • Selecting the optimal trace geometry design for minimal signal loss
  • Matched P&N intra-pair die-to-die (minimal mode conversion)
  • Using laminate fiber weave-aware PCB routing for minimal P&N skew
  • Simulated SerDes parameter optimization (ADS), compliant with ASIC vendor rules
  • In-System SerDes parameter optimization (scanned eye and binning)
  • Reduced dispersion and signal propagation disturbances (homogeneous Dk/Df)

PAM4 PCBs in New 400 Gbps Products

With Ethernet standards moving from NRZ to PAM4 encoding to reach a 50 Gbps lane rate and achieve 400 Gbps links, there was always going to be challenges for signal integrity engineers dealing with new PCB designs. Fortunately, with engineering experience, knowledge, and significant expertise, the challenges are being overcome as new 400 Gbps switch products start to reach the market.

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